The present invention relates to a semiconductor device which includes a plurality of vertical field effect transistors and wherein the field effect transistors are provided side by side with one another, and a manufacturing method thereof.
DMOS transistors each corresponding to a vertical field effect transistor have been known as semiconductor elements each of which enables large current to flow therethrough and is capable of being operated at a high voltage. The DMOS transistor allows current to flow between a source electrode formed on a major surface of a semiconductor substrate and a drain electrode formed on a back surface of the semiconductor substrate. A P-type base region is formed in its corresponding surface layer portion on the major surface side of the N-type semiconductor substrate, and an N-type source region is formed in its corresponding surface layer portion of the P-type base region. A source electrode is formed so as to contact the P-type base region and the N-type source region. A gate electrode is formed over the P-type base region through a gate insulating film interposed therebetween. When a positive electrode is applied to the gate electrode, an inversion-type channel is formed in its corresponding surface layer of the P-type base region. The current flows from the semiconductor substrate to the N-type source region and the source electrode via the channel. Since no channel is formed when the positive voltage is not applied to the gate electrode, no current flows. When the positive voltage is not applied to the gate electrode, a reverse bias is applied to a PN junction between the P-type base region and the N-type semiconductor substrate due to the voltage applied between the source and drain electrodes, so that a depletion layer spreads. The voltage applied between the source electrode and the drain electrode is applied to the depletion layer, but not applied to the gate insulating film. Therefore, a high breakdown voltage can be realized (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-318397)).
In each DMOS transistor referred to above, the depletion layer spreads due to the reverse bias applied to the PN junction between the P-type base region and the N-type semiconductor substrate. The voltage between the source and drain electrodes is applied to the depletion layer, but not applied to the gate insulating film. Since the DMOS transistor allows current to flow in the direction vertical to the semiconductor substrate, it is possible to cause large current to flow by providing a large number of the DMOS transistors side by side. In this case, the resistance of a current flowing region can be reduced by spreading or expanding the interval between the DMOS transistors, thus making it possible to cause more current to flow. On the other hand, when the interval between the DMOS transistors is spread, such a region that the depletion layer that spreads from the PN junction between the P-type base region and the N-type semiconductor substrate is not connected to its corresponding depletion layer that spreads from a PN junction of the adjoining DMOS transistor appears. Since the voltage between the source and drain electrodes is applied to the gate insulating film in the region in which the depletion layers are not connected to each other, a breakdown voltage is reduced. It is feared that no depletion layers are connected to each other particularly in a region increasing with distance from P-type base regions, such as a region surrounded by at least three DMOS transistors adjacent to one another, thus causing a reduction in breakdown voltage.